The invention relates to a global planarization process for integrated semiconductor circuits or micromechanical components having large-area regions of various heights and a step to be planarized between a higher-lying region and a lower-lying region, as well as a corresponding arrangement.
In semiconductor technology and in micromechanics (including sensor technology), the problem is known that, during the course of producing the components, there are formed regions of various heights which are relatively large in area (&gt;1000 .mu.m2), the step existing between the regions having to be planarized.
An example of this is that of integrated semiconductor circuits, in which the individual circuit elements such as transistors and capacitors have to be connected to one another with low resistance after their production. This is generally performed with the aid of single-layer or multi-layer metallization patterns, which are produced by depositing a metal layer over the entire surface and subsequently delineating patterns photolithographically to form conductor tracks. For an electrically reliable metallization pattern, it is necessary that, before depositing the metal layer, the underlying surface is as plain as possible, i.e. does not have any sharp edges, and that the difference in height is within the depth of focus of the photolithographic procedure used.
The second condition in particular is often difficult to satisfy when there is increasing integration density of the circuit, since a lateral reduction in size in many cases requires an increase in the vertical dimension. For instance, in the case of DRAM semiconductor memories, to increase the integration density memory cells of the "stacked-capacitor" or "stacked-capacitor-above-bitline" type are used, as are described for example in the article by T. Kaga in IEEE Transactions on ED, volume 38, No. 2, February 1991, page 255, in which the capacitor provided on top causes a step between relatively large-area (order of magnitude 100 .mu.m.times.100 .mu.m) regions, namely the cell array and the lower-lying periphery containing the wiring. Such a step cannot be smoothed out by conventional, local planarization processes. A particularly high step occurs if, to increase capacitance, a so-called crown capacitor is used.
The metal layer mentioned must provide electrical contact for various conductive structures which are arranged on various levels (for example substrate, wordline level, bitline level, capacitor), by contact holes being etched into an insulating layer separating the metallization pattern and the conductive structures and being filled with a conductive material. It is advantageous if the layer thicknesses of the insulating layer to be etched through in this case are known precisely, in order to avoid lengthy overetching times and to permit so-called "non-nested contacts".